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K6F3216U6M Family
Document Title
2M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 0.1 Initial draft Revised - Changed ICC2 from 35mA to 40mA for 55ns product from 25mA to 35mA for 70ns product - Changed ISB1 from 30A to 40A - Changed IDR from 15A to 20A Finalize
Draft Date
January 31, 2002 July 30, 2002
Remark
Preliminary Preliminary
1.0
December 18, 2002
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 December 2002
K6F3216U6M Family
FEATURES
* Process Technology: Full CMOS * Organization: 2M x16 * Power Supply Voltage: 2.7~3.3V * Low Data Retention Voltage: 1.5V(Min) * Three State Outputs * Package Type: 55-TBGA-7.50x12.00
CMOS SRAM
GENERAL DESCRIPTION
The K6F3216U6M families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
2M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PRODUCT FAMILY
Power Dissipation Product Family K6F3216U6M-F Operating Temperature Industrial(-40~85C) Vcc Range 2.7~3.3V Speed 551)/70ns Standby (ISB1, Max.) 40A Operating (ICC1, Max) 7mA PKG Type 55-TBGA-7.50x12.00
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
1 2 3 4 5 6 7 8
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
A B C D E F G H J K L M
N.C
N.C
Vcc Vss Row Addresses
N.C
LB
OE
A0
A1
A2
CS2
Row select
Memory Cell Array
I/O9
UB
A3
A4
CS1
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vss
I/O12
A17
A7
I/O4
Vcc
I/O1~I/O8
Data cont Data cont Data cont
I/O Circuit Column select
Vcc
I/O13
N.C
A16
I/O5
Vss
I/O9~I/O16
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
A19
A12
A13
WE
I/O8
Column Addresses
A18
A8
A9
A10
A11
A20 CS1 CS2
N.C
N.C
N.C
N.C
OE WE UB LB
Control Logic
55-TBGA: Top View (Ball Down)
Name CS1, CS2 OE WE A0~A20
Function Chip Select Inputs Output Enable Input Write Enable Input Address Inputs
Name Vcc Vss UB LB N.C
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) No Connection
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.0 December 2002
K6F3216U6M Family
PRODUCT LIST
Industrial Temperature Products(-40~85C) Part Name K6F3216U6M-EF55 K6F3216U6M-EF70 Function 55-TBGA, 55ns, 3.0V 55-TBGA, 70ns, 3.0V
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS1 H X1) X1) L L L L L L L L CS2 X1) L X1) H H H H H H H H OE X1) X1) X1) H H L L L X
1)
WE X1) X1) X1) H H H H H L L L
LB X1) X1) H L X1) L H L L H L
UB X1) X1) H X1) L H L L H L L
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
X1) X
1)
1. X means dont care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V(Max. 3.6V) -0.2 to 3.6 1.0 -65 to 150 -40 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability.
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Revision 1.0 December 2002
K6F3216U6M Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.3
3)
CMOS SRAM
Typ 3.0 0 Max 3.3 0 Vcc+0.3 0.6
2)
Unit V V V V
Note: 1. TA=-40 to 85C, otherwise specified 2. Overshoot: VCC+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and Undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current
Symbol
Test Conditions VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to Vcc Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, LB0.2V or/and UB0.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA Other input =0~Vcc 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0VCS20.2V(CS2 controlled) 70ns 55ns
Min -1 -1 2.4 -
Typ 1) -
Max 1 1 7 35 40 0.4 40
Unit A A mA mA V V A
ILI ILO ICC1
Average operating current ICC2 Output low voltage Output high voltage Standby Current (CMOS) VOL VOH ISB1
1. Typical values are measured at VCC=3.0V, TA=25C and not 100% tested.
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Revision 1.0 December 2002
K6F3216U6M Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V
AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85C )
Speed Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output UB, LB valid to data output Read Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write UB, LB Valid to End of Write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH tWC tCW1, tCW2 tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 55 10 10 5 0 0 0 10 55 45 0 45 45 40 0 0 25 0 5 55ns Max 55 55 25 55 20 20 20 20 Min 70 10 10 5 0 0 0 10 70 60 0 60 60 50 0 0 30 0 5 70ns Max 70 70 35 70 25 25 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V , VIN0V Vcc=1.5V, CS1Vcc-0.2V , VIN0V See data retention waveform
1) 1)
Min 1.5 0 tRC
Typ -
Max 3.3 20 -
Unit V A ns
1. 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0CS20.2V(CS2 controlled)
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Revision 1.0 December 2002
K6F3216U6M Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
tRC Address tAA tCO tOH
CS1
CS2 tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 December 2002
K6F3216U6M Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tWR(4)
CMOS SRAM
CS2 tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z
UB, LB
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 1.0 December 2002
K6F3216U6M Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS1 tAW CS2 tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
CMOS SRAM
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 2.7V tSDR Data Retention Mode tRDR
2.2V VDR CS1VCC - 0.2V
CS1 GND
CS2 controlled
VCC 2.7V CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND CS20.2V
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Revision 1.0 December 2002
K6F3216U6M Family
PACKAGE DIMENSION
55 BALL TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View Bottom View B B 8 #A1 A B C D E 7 6 5 4 3 B/2 2 1
CMOS SRAM
Unit: millimeters
C1 B1 Detail A A 0.35/Typ. Y Notes. 1. Bump counts: 55(12 row x 8 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are 0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max)
C
G H C1/2 J K L M
Side View
D
C
Min A B B1 C C1 D E E1 E2 Y 7.40 11.90 0.40 0.80 0.30 -
Typ 0.75 7.50 5.25 12.00 8.25 0.45 0.90 0.55 0.35 -
Max 7.60 12.10 0.50 1.00 0.40 0.08
9
0.55/Typ.
Revision 1.0 December 2002
C
F
E2
E1 E

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